T
T
T
S
S
S
3
3
3
2
2
2
M
M
M
L
L
L
S
S
S
7
7
7
2
2
2
V
V
V
6
6
6
D
D
D
168PIN PC133 Unbuffered DIMM
256MB With 16Mx8 CL3
SIMPLIFIED TRUTH TABLE
3
X X
X
H
COMMAND CKEn-1 CKEn
H
Both Banks
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
/CS /RAS /CAS /WE
H
4, 5
Write &
L H H
Note:
1. OP Code : Operand Code
DQM BA
0,1
A
10
/AP
X X X
Auto Precharge Disable
Column Address
H
X H
H
A
0
~A
11
, BA
0
~BA
1
: Program keys. (@MRS)
A
11
, A
0
~A
9
Note
3
X L H
2. MRS can be issued only at both banks precharge state.
Register Mode Register Set H X
Bank Active & Row Addr. H X
L L X V
Entry
H
Clock Suspend or
Active Power
Down
H
Exit
L H
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
L L L
L L H
L
Column
Address
H X
L
X X X
The automatically precharge without row precharge command is meant by “Auto”.
L X OP CODE
H X V
4
(A
0
~A
8
)
X X
X
X
Auto/self refresh can be issued only at both banks precharge state.
1,2
Auto Refresh
Refresh
Row Address
Auto Precharge Enable
X
4. BA
0
~BA
1
: Bank select address.
H
H L
L V
If both BA
0
and BA
1
are “Low” at read, write, row active and precharge, bank A is selected.
3
X X
H
4, 5
V
DQM
If both BA
0
is “High” and BA
1
is “Low” at read, write, row active and precharge, bank C is selected.
Entry L
Auto Precharge Disable
H X
H
L L H
L V V
V V
If both BA
0
is “Low” and BA
1
is “High” at read, write, row active and precharge, bank B is selected.
3
L
H X V
6
Bank Selection
Precharge
X
H X X X
New row active of the associated bank can be issued at tRP after the end of burst.
L H H H
Auto Precharge Enable
V L
X X
X X X
X
L H H
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Self
Refresh
Exit
L H
4
L H L
H
H L
7. DQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
Read &
Column Address
Burst Stop H X
Exit
H X V
If both BA
0
and BA
1
are “High” at read, write, row active and precharge, bank D is selected.
L H L
L X X
X X
Column
Address
(A
0
~A
8
)
H X L
Entry
Precharge Power
Down Mode
X X
6. Burst stop command is valid at every burst length.
L H
L H
X
X 7
If A
10
/AP is “High” at row precharge, BA
0
and BA
1
are ignored and both banks are selected.
X
No Operation Command
H X
5. During burst read or write with auto precharge, new read/write command cannot be issued.
Another bank read/write command can be issued after the end of burst.
Transcend Information Inc.
9
(11 pages)
(1 pages)
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