Transcend TS64MSD64V3J Datasheet download pdf (Page 9)

200PIN DDR333 Unbuffered SO-DIMM

512MB With 64Mx8 CL2.5

Transcend Information Inc.

DQ & DM hold time to DQS tDH 0.45 ns

DQ & DM input pulse width tDIPW 1.75 ns

Power down exit time tPDEX 6 Ns

Exit self refresh to bank active command tXSA 75 ns 5

Exit self refresh to read command tXSR 200 Cycle

Refresh interval time tREF 7.8 us 1

Clock half period tHP TCLmin or

tCHmin

Data hold skew factor tQHS 0.75 Ns

DQS write postamble time tWPST 0.4 0.6 TCK 3

Note: 1. Maximum burst refresh of 8

2. The specific requirement is that DQS be valid(High or Low) on or before this CK edge. The case shown

(DQS going from High_Z to logic Low) applies when no writes were previously in progress on the bus. If a

previous write was in progress, DQS could be High at this time, depending on tDQSS.

3. The Maximum limit for this parameter is not a device limit. The device will operate with a great value for this

parameter, but system performance (bus turnaround) will degrade accordingly.

4. For registered DIMMs, tCL and tCH are >= 45% of the period including both the half period jitter (tJIT(HP) ) of

the PLL and the half period jitter due to crosstalk (tJIT(crosstalk)) on the DIMM.

5. A write command can be applied with tRCD satisfied after this command.

1 2 3 4 5 6 7 8 9 10 11 12

No comments

Transcend TS64MSD64V3J Datasheet Page 9