Transcend TS64MDR72V6L5 Datasheet download pdf (Page 7)

184Pin DDR266 Registered DIMM

512MB with 64Mx4 CL2.5

AC OPERATING CONDITIONS

Parameter Symbol Min Max

Unit Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH (AC) VREF + 0.31 V 3

Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL (AC) VREF - 0.31 V 3

Input Differential Voltage, CK and /CK inputs VID (AC) 0.7 VDDQ + 0.6 V 1

Input Crossing Point Voltage, CK and /CK inputs VIX (AC) 0.5*VDDQ - 0.2 0.5*VDDQ + 0.2 V 2

Note: 1. VID is the magnitude of the difference between the input level on CK and the input on /CK.

2. The value of VIX is expected to equal 0.5*V DDQ of the transmitting device and must track variations in the DC

level of the same.

3. These parameters should be tested at the pin on actual components and may be checked at either the pin or

the pad in simulation the AC and DC input specifications are relative to a VREF envelope that has been

bandwidth limited 20MHz.

AC OPERATING TEST CONDITIONS (VDD=2.5, VDDQ=2.5, TA=0 to 70°C)

Parameter Value Unit Note

Input reference voltage for Clock 0.5*VDDQ V

Input signal maximum peak swing 1.5 V

Input Levels (VIH/VIL) VREF+0.31/VREF-0.31 V

Input timing measurement reference level VREF V

Output timing measurement reference level VTT V

Output load condition See Load Circuit

ZO=50ohm

VTT=0.5*VDDQ

RT=50ohm

LOAD

=30pF

Output

Output Load circuit

VREF

=0.5*VDDQ

Input/Output CAPACITANCE (VDD = 2.5V, VDDQ = 2.5V,TA = 25°C, f = 1MHz)

Parameter Symbol Min Max Unit

Input capacitance (A0~A12, BA0~BA1, /RAS, /CAS, /WE)

Input capacitance (CKE0)

Input capacitance (/CS0)

Input capacitance (CLK0, /CLK0)

Data and DQS input/output capacitance (DQ0~DQ63)

Input capacitance (DM0~DM8)

Data input/output capacitance (CB0~CB7)

IN1

CIN2

CIN3

IN4

CIN5

COUT1

COUT2

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