Transcend TS64MDR72V6L5 Datasheet download pdf (Page 10)

184Pin DDR266 Registered DIMM

512MB with 64Mx4 CL2.5

Serial Presence Detect Specification

Serial Presence Detect

Byte No. Function Described Standard Specification Vendor Part

0 # of Bytes Written into Serial Memory 128bytes 80

1 Total # of Bytes of S.P.D Memory 256bytes 08

2 Fundamental Memory Type DDR SDRAM 07

3 # of Row Addresses on this Assembly 13 0D

4 # of Column Addresses on this Assembly 11 0B

5 # of Module Rows on this Assembly 1 bank 01

6 Data Width of this Assembly 72bits 48

7 Data Width of this Assembly 0 00

8 VDDQ and Interface Standard of this Assembly SSTL 2.5V 04

9 DDR SDRAM Cycle Time at CAS Latency=2.5 7.5ns 75

10 DDR SDRAM Access Time from Clock at CL=2.5 0.75ns 75

11 DIMM configuration type (non-parity, Parity, ECC) ECC 02

12 Refresh Rate Type 7.8us/Self Refresh 82

13 Primary DDR SDRAM Width X4 04

14 Error Checking DDR SDRAM Width X4 04

15 Min Clock Delay for Back to

Back Random Column Address

tCCD=1CLK 01

16 Burst Lengths Supported 2,4,8 0E

17 # of banks on each DDR SDRAM device 4 bank 04

18 CAS Latency supported 2, 2.5 0C

19 CS Latency 0 CLK 01

20 WE Latency 1 CLK 02

21 DDR SDRAM Module Attributes

Registered address &

control inputs and

on-card DLL

22 DDR SDRAM Device Attributes: General +/-0.2V voltage tolerance 00

23 DDR SDRAM Cycle Time CL=2.0 10ns A0

24 DDR SDRAM Access from Clock CL=2.0 0.75ns 75

25 DDR SDRAM Cycle Time CL=1.5 - 00

26 DDR SDRAM Access from Clock CL=1.5 - 00

27 Minimum Row Precharge Time (tRP) 20ns 50

28 Minimum Row Active to Row Activate delay (tRRD) 15ns 3C

29 Minimum RAS to CAS Delay (tRCD) 20ns 50

30 Minimum active to Precharge time (tRAS) 45ns 2D

31 Module ROW density 512MB 80

32 Command/Address Input Setup Time 0.9ns 90

33 Command/Address Input Hold Time 0.9ns 90

34 Data Signal Input Setup Time 0.5ns 50

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