Transcend TS128MSD64V6A Datasheet download pdf (Page 7)

200PIN DDR266 Unbuffered SO-DIMM

1GB With 64Mx8 CL2.5

AC OPERATING CONDITIONS

Parameter Symbol

Input Levels (VIH/VIL)

Min Max

Unit

VREF+0.31/VREF-0.31 V

Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals

Input timing measurement reference level VREF

VIH(AC) VREF + 0.31 V

Output timing measurement reference level

Input Low (Logic 0) Voltage, DQ, DQS and DM signals

VIL(AC) VREF - 0.31

Output load condition See Load Circuit

V 3

Input Differential Voltage, CK and /CK inputs

VID(AC) 0.7 VDDQ + 0.6

Input/Output CAPACITANCE

(VDD = 2.5V, VDDQ = 2.5V,TA = 25°C, f = 1MHz)

Parameter Symbol

V 1

Min Max Unit

Input Crossing Point Voltage, CK and /CK inputs VIX(AC) 0.5*VDDQ - 0.2

Input capacitance (A0~A12, BA0~BA1, /RAS, /CAS, /WE)

Input capacitance (CKE0,CKE1)

Input capacitance (/CS0,/CS1)

0.5*VDDQ + 0.2 V 2

Input capacitance (CK0, CK1)

Input capacitance (DM0~DM7)

Data and DQS input/output capacitance (DQ0~DQ63)

Note: 1. VIH(max)=4.2V. The overshoot voltage duration is <=3ns at VDD.

IN1

CIN2

IN3

2. VIL(min)=-1.5V. The undershoot voltage duration is <=3ns at VSS

IN4

CIN5

COUT1

3. VID is the magnitude of the difference between the input level on CK and the input on /CK

4. The Value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the

DC level of the same.

AC OPERATING TEST CONDITIONS

(VDD=2.5, VDDQ=2.5, TA=0 to 70°C)

Parameter Value

Unit Note

Input reference voltage for Clock

0.5*VDDQ V

Input signal maximum peak swing 1.5

VTT V

ZO=50ohm

VTT=0.5*VDDQ

RT=50ohm

LOAD

=30pF

Output

Output Load circuit

VREF

=0.5*VDDQ

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