T
T
T
S
S
S
1
1
1
2
2
2
8
8
8
M
M
M
S
S
S
D
D
D
6
6
6
4
4
4
V
V
V
6
6
6
A
A
A
200PIN DDR266 Unbuffered SO-DIMM
1GB With 64Mx8 CL2.5
Serial Presence Detect Specification
75
11 DIMM configuration type (non-parity, Parity, ECC)
23 DDR SDRAM Cycle Time CL=2.0 10.0ns
0.5ns 50
36-40
Serial Presence Detect
Byte No. Function Described
NON-ECC 00
A0
24
Superset Information - 00
Standard
Specification
Vendor Part
12 Refresh Rate Type 7.8us/Self Refresh
DDR SDRAM Access from Clock CL=2.0
±0.75ns
75
41
DDR SDRAM Minimum Active / Auto Refresh
Time(tRC)
0 # of Bytes Written into Serial Memory 128bytes
82
13 Primary DDR SDRAM Width
25 DDR SDRAM Cycle Time CL=1.5 -
- 00
80
1 Total # of Bytes of S.P.D Memory
X8 08
00
26
256bytes 08
14 Error Checking DDR SDRAM Width -
DDR SDRAM Access from Clock CL=1.5 - 00
2 Fundamental Memory Type DDR SDRAM 07
3 # of Row Addresses on this Assembly 13 0D
0B
00
15 Min Clock Delay for Back to
Back Random Column Address
tCCD=1CLK 01
16
17 # of banks on each DDR SDRAM device 4 bank
27 Minimum Row Precharge Time (tRP) 20ns 50
28 Minimum Row Active to Row Activate delay (tRRD) 15ns
20ns 50
30 Minimum active to Precharge time (tRAS)
4 # of Column Addresses on this Assembly 11
Burst Lengths Supported 2,4,8 0E
3C
29 Minimum RAS to CAS Delay (tRCD)
5 # of Module Rows on this Assembly 2bank 02
04
18 CAS Latency supported
45ns 2D
6 Data Width of this Assembly 64bits
2.5 , 2 0C
31 Module ROW density
40
7 Data Width of this Assembly
19 CS Latency 0 CLK 01
512MB 80
32
0 00
20 WE Latency
Command/Address Input Setup Time 0.9ns 90
8 VDDQ and Interface Standard of this Assembly SSTL-2
1 CLK 02
33 Command/Address Input Hold Time
04
9 DDR SDRAM Cycle Time at CAS Latency=2.5
21 DDR SDRAM Module Attributes
Differential
Clock Input
0.9ns 90
34
7.5ns 75
20
22
Data Signal Input Setup Time 0.5ns 50
10 DDR SDRAM Access Time from Clock at CL=2.5
±0.75ns
DDR SDRAM Device Attributes: General Fast / current AP 00
35 Data Signal Input Hold Time
Transcend Information Inc.
11
(11 pages)
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