Transcend TS32MMQ64V5M Datasheet download pdf (Page 7)

214PIN DDR2 533 Micro-DIMM

256MB With 32Mx16 CL4

Input AC Logic Level

Parameter Symbol Min Max

Unit Note

Input High (Logic 1) Voltage, DQ, DQS and DM signals VIH(AC) VREF + 0.250 V

Input Low (Logic 0) Voltage, DQ, DQS and DM signals VIL(AC) VREF - 0.250 V

AC Input Test Condition

Condition Symbol Value Unit Note

Input reference voltage VREF 0.5*VDDQ V 1

Input signal maximum peak to peak swing VSWING(MAX) 1.0 V 1

Input signal minimum slew rate SLEW

1.0 V/ns 2,3

1. Input waveform timing is referenced to the input signal crossing through the VIH/IL(AC) level applied to the

device under test.

2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(AC) min for rising

edges and the range from VREF to VIL(AC) max for falling edges as shown in the below figure.

Note:

3. AC timings are referenced with input waveforms switching from VIL(AC) to VIH(AC) on the positive transitions

and VIH(AC) to VIL(AC) on the negative transitions.

SWING(MAX)

delta TF

delta TR

VDD

(AC)

min

(DC)

min

VREF

(DC)

max

(AC)

max

VSS

Falling Slew=

VREF-VIL(AC)max

delta TF

Rising Slew=

VIH(AC)min-VREF

delta TR

AC Input Test Signal Waveform

Input/Output Capacitance

(VDD = 1.8V, VDDQ = 1.8V, TA = 25°C)

Parameter Symbol Min Max Unit

Input capacitance (CK0 and /CK0)

Input capacitance (CK1 and /CK1)

Input capacitance (CKE and /CS)

Input capacitance (A0~A13, BA0~BA2, /RAS, /CAS, /WE)

Input capacitance (DQ, DM, DQS, /DQS)

CCK0

CCK1

CI2

CIO

Note:

DM is internally loaded to match DQ and DQS identically.

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