Transcend TS32GSSD25H-M Datasheet download pdf (Page 3)

2.5” Half-Slim

Solid State Disk

Transcend Information Inc.

Preliminary V0.7

Reliability

Reliability Reliability

Reliability

Wear-Leveling algorithm

The controller supports static/dynamic wear leveling. When the host writes data, the controller will find and use the block

with the lowest erase count among the free blocks. This is known as dynamic wear leveling. When the free blocks' erase

count is higher than the data blocks', it will activate the static wear leveling, replacing the not so frequently used user

blocks with the high erase count free blocks.

ECC algorithm

The controller uses BCH8/BCH15 ECC algorithm per 512 bytes according to structure of flash. BCH8/BCH15 can correct

up to 8 or 15 random error bits within 512 data bytes.

Bad-block management

When the flash encounters ECC failed, program fail or erase fail, the controller will mark the block as bad block to prevent

the used of this block and caused data lost later on.

Actual Capacity

Model P/N User Max. LBA Cylinder Head Sector

TS8GSSD25H-M 15,621,984 15,498 16 63

TS16GSSD25H-M 31,277,056 16,383 16 63

TS32GSSD25H-M 62,586,880 16,383 16 63

TS64GSSD25H-M 125,206,528 16,383 16 63

Reliability

Data Reliability

Supports BCH ECC 8 bits/ 15 bits in 512 bytes

Data Retention

10 years

MTBF

1,500,000 hours

Regulations

Compliance

CE, FCC and BSMI

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Transcend TS32GSSD25H-M Datasheet Page 3