T
T
T
S
S
S
1
1
1
6
6
6
M
M
M
L
L
L
R
R
R
7
7
7
2
2
2
V
V
V
6
6
6
D
D
D
168PIN PC133 Registered DIMM
128MB With 16Mx8 CL3
SIMPLIFIED TRUTH TABLE
COMMAND SCKEn-1 SCKEn /SCS /SRAS /SCAS /SWE SDQM SBA0,1 SA10/AP SA11,SA0~SA9 Note
Register Mode Register Set H X L L L L X OP CODE 1,2
Auto Refresh H 3
Entry
H
L
L L L H X X
3
L H H H 3
Refresh
Self
Refresh
Exit L H
H X X X
X X
3
Bank Active & Row Addr. H X L L H H X V Row Address
Auto Precharge Disable L 4
Read &
Column Address
Auto Precharge Enable
H X L H L H X V
H
Column
Address
(SA
0~SA9)
4, 5
Auto Precharge Disable L 4
Write &
Column Address
Auto Precharge Enable
H X L H L L X V
H
Column
Address
(SA
0~SA9)
4, 5
Burst Stop H X L H H L X X 6
Bank Selection V L
Precharge
All Banks
H X L L H L X
X H
X
H X X X
Entry H L
L V V V
X
Clock Suspend or
Active Power Down
Exit L H X X X X X
X
H X X X
Entry
H L
L H H H
X
H X X X
Precharge Power
Down Mode
Exit
L H
L V V V
X
X
SDQM H X V X 7
H X X X
No Operation Command
H X
L H H H
X X
(V=Valid, X=Don’t Care, H=Logic High, L=Logic Low)
Note: 1. OP Code : Operand Code
SA0~SA11, SBA0~SBA1 : Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by “Auto”.
Auto/self refresh can be issued only at both banks precharge state.
4. SBA0~SBA1: Bank select address.
If both SBA0 and SBA1 are “Low” at read, write, row active and precharge, bank A is selected.
If both SBA0 is “Low” and SBA1 is “High” at read, write, row active and precharge, bank B is selected.
If both SBA0 is “High” and SBA1 is “Low” at read, write, row active and precharge, bank C is selected.
If both SBA0 and SBA1 are “High” at read, write, row active and precharge, bank D is selected.
If SA10/AP is “High” at row precharge, SBA0 and SBA1 is ignored and both banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. SDQM sampled at positive going edged of a CLK masks the data-in at the very CLK (Write SDQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read SDQM latency is 2)
Transcend Information Inc. 8
(12 pages)
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