T
T
T
S
S
S
1
1
1
2
2
2
8
8
8
M
M
M
S
S
S
D
D
D
6
6
6
4
4
4
V
V
V
3
3
3
A
A
A
200PIN DDR333 Unbuffered SO-DIMM
1GB With 64Mx8 CL2.5
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted,VDD=2.7V TA = 10°C)
Operating current - burst write; Burst length = 2; writes; continuous burst; One
bank active address and control inputs changing once per clock cycle; CL=2.5 at
tCK = tCK min ; DQ, DM and DQS inputs changing twice per clock cycle, 50% of
input data changing at every burst
IDD4W 1,720
Parameter Symbol Max.
mA
Unit Note
Auto refresh current; tRC = tRFC(min)
IDD5 3,429
Operating current - One bank Active-Precharge;
tRC=tRCmin; tCK= tCK min
DQ, DM and DQS inputs changing twice per clock cycle;
Address and control inputs changing once per clock cycle
mA
Self refresh current; CKE <= 0.2V;
IDD0 1466 mA
IDD6 64 mA
Operating current - One bank Active-Read-Precharge; Burst=2;
Operating current - Four bank operation;
tRC=tRC min; CL=2.5; tCK=tCK min; VIN=VREF fro DQ,DQS and DM
IDD1 1625 mA
Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
IDD7 3,774
Percharge power-down standby current; All banks idle;
mA
power –down mode; CKE = <VIL(max); tCK= tCK min
VIN = VREF
for DQ,DQS and DM
IDD2P
Note: 1. Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ
loading capacitor.
165 mA
Precharge Floating standby current; CS# > =VIH(min);All banks idle;
CKE > = VIH(min); tCK=166Mhz for DDR333
Address and other control inputs changing once per clock cycle;
VIN = VREF for DQ,DQS and DM
IDD2F 533 mA
Active power - down standby current ; one bank active; power-down mode; CKE<=
VIL (max); tCK = tCK min;
VIN = VREF for DQ,DQS and DM
IDD3P 214 mA
Active standby current; CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK = tCK min;
DQ, DQS and DM inputs changing twice per clock cycle; address and other control
inputs changing once per clock cycle
IDD3N 765 mA
Operating current - burst read; Burst length = 2; reads; continguous burst; One
bank active; address and control inputs changing once per clock cycle; CL=2.5 at
tCK = tCK min ; 50% of data changing at every burst; lout = 0 mA
IDD4R 1,840 mA
Transcend Information Inc.
6
(13 pages)
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