Transcend TS1GSH72V1H Datasheet

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1
260Pin DDR4 2133 ECC SO-DIMM
8GB Based on 512Mx8
TS1GSH72V1H
Description
DDR4 ECC SO-DIMMs are high-speed, low power
memory modules that use 512Mx8bits DDR4 SDRAM in
FBGA package and a 4K-bit serial EEPROM on a 260-pin
printed circuit board. DDR4 ECC SO-DIMMs are Dual
In-Line memory modules and are intended for mounting
into 260-pin edge connector sockets.
The synchronous design allows precise cycle control with
the use of system clock. Data I/O transactions are
possible on both edges of DQS. The large range of
operation frequencies and programmable latencies allow
the same device to be useful for a variety of high
bandwidth and high performance memory system
applications.
Features
RoHS compliant
JEDEC standard 1.2V ± 0.06V power supply
VDDQ=1.2V ± 0.06V
Clock Freq: 1067MHZ for 2133Mb/s/Pin.
Programmable CAS Latency: 10,11,12,13,14,15,16
Programmable Additive Latency (Posted /CAS):
0,CL-2 or CL-1 clock
Programmable /CAS Write Latency (CWL)
= 11, 14(DDR4-2133)
8 bit pre-fetch
Burst Length: 4, 8
Bi-directional Differential Data-Strobe
On Die Termination with ODT pin
Serial presence detect with EEPROM
On DIMM Thermal Sensor
Asynchronous reset
Pin Identification
Symbol
Function
A0A14
SDRAM address bus
BA0, BA1
SDRAM bank select
BG0, BG1
SDRAM bank group select
RAS_n
SDRAM row address strobe
CAS_n
SDRAM column address strobe
WE_n
SDRAM write enable
CS0_n, CS1_n
DIMM Rank Select Lines
CKE0, CKE1
SDRAM clock enable lines
ODT0, ODT1
SDRAM on-die termination control
lines
ACT_n
SDRAM activate
DQ0DQ63
DIMM memory data bus
CB0CB7
DIMM ECC check bits
DM_n/DBI_n/
Input data mask and data bus
inversion
DQS0_tDQS8_t
SDRAM data strobes
(positive line of differential pair)
DQS0_cDQS8_c
SDRAM data strobes
(negative line of differential pair)
CK0_t, CK1_t
SDRAM clocks
(positive line of differential pair)
CK0_c, CK1_c
SDRAM clocks
(negative line of differential pair)
PARITY
SDRAM parity input
VDD
SDRAM I/O and core power supply
VREFCA
SDRAM command/address
reference supply
VSS
Power supply return (ground)
VDDSPD
Serial SPD EEPROM positive
power supply
SCL
I
2
C serial bus clock for EEPROM
SDA
I
2
C serial bus data line for
EEPROM
SA0SA2
I
2
C slave address select for
EEPROM
ALERT_n
SDRAM ALERT_n
VPP
SDRAM Supply
RESET_n
Set DRAMs to a Known State
EVENT_n
SPD signals a thermal event has
occurred
VTT
SDRAM I/O termination supply
RFU
Reserved for future use
NC
No Connection
NF
No function
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Summary of Contents

Page 1

1 260Pin DDR4 2133 ECC SO-DIMM 8GB Based on 512Mx8 TS1GSH72V1H Description DDR4 ECC SO-DIMMs are high-speed, low power memory modules that

Page 2

10 SERIAL PRESENCE DETECT SPECIFICATION TS1GSH72V1H Serial Presence Detect Byte No. Function Described Standard Specification Vendor Part 0 Numbe

Page 3 - Pin Assignments

11 78-116 Reserved - 00 117 Fine Offset for Minimum CAS to CAS Delay Time (tCCD_Lmin), same bank group - EC 118 Fine Offset for Minimum Activate

Page 4

2 Dimensions (Unit: millimeter) Note: 1. Tolerances on all dimensions +/-0.15mm unless otherwise specified.

Page 5

3 Pin Assignments Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name Pin No Pin Name 01 VSS 89 VSS 177 DQS4_c 02 VSS

Page 6

4 Block Diagram 8GB, 1Gx72 Module(2 Rank x8) This technical information is based on industry standard d

Page 7

5 Operating Temperature Condition Parameter Symbol Rating Unit Note Operating Temperature TOPER 0 to 85 C 1,2 Note:  Operating Temperature is

Page 8

6 Differential AC and DC Input Levels Parameter Symbol DDR4-1600/1866/2133 Unit Note Min Max differential input high DC VIHdiff(DC) +0.150 NOTE 3

Page 9

7 IDD Specification parameters Definition ( IDD values are for full operating range of Voltage and Temperature) 8GB, 1Gx72 Module(2 Rank x8) Para

Page 10

8 Timing Parameters & Specifications Speed DDR4 2133 Unit Parameter Symbol Min Max Average Clock Period tCK 0.938 <1.071 ns CK high-level

Page 11

9 Speed DDR4 2133 Unit Parameter Symbol Min Max CAS_n to CAS_n command delay for different bank group tCCD_S 4 - nCK Auto precharge write recover

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